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HI5808
Data Sheet February 1999 File Number 4233.4
12-Bit, 10 MSPS A/D Converter
The HI5808 is a monolithic, 12-bit, Analog-to-Digital Converter fabricated in Intersil's HBC10 BiCMOS process. It is designed for high speed, high resolution applications where wide bandwidth and low power consumption are essential. The HI5808 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (S/H). The HI5808 has excellent dynamic performance while consuming 325mW power at 10 MSPS. The 100MHz full power input bandwidth is ideal for communication systems and document scanner applications. Data output latches are provided which present valid data to the output bus with a latency of 3 clock cycles. The digital outputs have a separate supply pin which can be powered from a 3V to 5V supply.
Features
* Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MSPS * Low Power * Internal Sample and Hold * Fully Differential Architecture * Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz * Low Distortion * Internal Voltage Reference * TTL/CMOS Compatible Digital I/O * Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
Applications
* Digital Communication Systems * Undersampling Digital IF
Ordering Information
PART NUMBER HI5808BIB HI5808EVAL1 SAMPLE RATE 10 MSPS TEMP. RANGE (oC) -40 to 85 25 PACKAGE 28 Ld SOIC PKG. NO. M28.3
* Document Scanners * Additional Reference Documents - AN9214 Using Intersil High Speed A/D Converters - AN9724 Using the HI5808EVAL1 Evaluation Board
Evaluation Board
Pinout
HI5808 (SOIC) TOP VIEW
CLK DVCC1 DGND1 DVCC1 DGND1 AVCC AGND VIN+ VIN1 2 3 4 5 6 7 8 9 28 D0 27 D1 26 D2 25 D3 24 D4 23 D5 22 DVCC2 21 DGND2 20 D6 19 D7 18 D8 17 D9 16 D10 15 D11
VDC 10 VROUT 11 VRIN 12 AGND 13 AVCC 14
117
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HI5808 Functional Block Diagram
VDC VINVIN+ S/H STAGE 1 DVCC2 BIAS CLOCK REF CLK VROUT VRIN
4-BIT FLASH +
4-BIT DAC
X8 DIGITAL DELAY AND DIGITAL ERROR CORRECTION
D11 (MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)
STAGE 3
4-BIT FLASH +
4-BIT DAC
X8
-
STAGE 4 4-BIT FLASH
DGND2
AVCC
AGND
DVCC1
DGND1
Typical Applications Schematic
(LSB) (28) D0 (27) D1 VROUT (11) (26) D2 (25) D3 VRIN (12) (24) D4 AGND (7) (23) D5 AGND (13) (20) D6 DGND1 (3) (19) D7 DGND1 (5) (18) D8 DGND2 (21) (17) D9 (16) D10 (MSB) (15) D11 VIN+ VIN+ (8) VDC (10) VINCLOCK VIN- (9) CLK (1) (4) DVCC1 (2) DVCC1 (22) DVCC2 0.1F (6) AVCC (14) AVCC HI5808 0.1F +5V + 10F + 10F +5V 10F AND 0.1F CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
DGND
AGND
BNC
118
HI5808
Absolute Maximum Ratings
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . +6.0V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5V, fS = 10 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC, Unless Otherwise Specified HI5808BIB -40oC TO 85oC
PARAMETER ACCURACY Resolution Integral Linearity Error, INL Differential Linearity Error, DNL (Guaranteed No Missing Codes) Offset Error, VOS Full Scale Error, FSE DYNAMIC CHARACTERISTICS Minimum Conversion Rate Maximum Conversion Rate Effective Number of Bits, ENOB Signal to Noise and Distortion Ratio, SINAD RMS Signal = ------------------------------------------------------------RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal = -----------------------------RMS Noise Total Harmonic Distortion, THD 2nd Harmonic Distortion 3rd Harmonic Distortion Spurious Free Dynamic Range, SFDR Intermodulation Distortion, IMD Transient Response Over-Voltage Recovery ANALOG INPUT Maximum Peak-to-Peak Differential Analog Input Range (VIN+ VIN-) Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RIN Analog Input Capacitance, CIN Analog Input Bias Current, IB+ or IBDifferential Analog Input Bias Current IB DIFF = (IB+ - IB-) Full Power Input Bandwidth, FPBW
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12 fIN = DC fIN = DC fIN = DC fIN = DC No Missing Codes No Missing Codes fIN = 1MHz fIN = 1MHz -
1 0.5 19 32
2 1 -
Bits LSB LSB LSB LSB
10 10.0 -
0.5 10.8 66.5
-
MSPS MSPS Bits dB
fIN = 1MHz
-
67.3
-
dB
fIN = 1MHz fIN = 1MHz fIN = 1MHz fIN = 1MHz f1 = 1MHz, f2 = 1.02MHz 0.2V Overdrive
-
-75 -80 -77 77 -65 1 2 2.0 4.0 10 0.5 100
-
dBc dBc
-
dBc dBc dBc Cycle Cycle
(Notes 2, 3) 1 (Note 3) -10 -
+10 -
V V M pF A A MHz
119
HI5808
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5V, fS = 10 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF, TA = -40oC to 85oC, Differential Analog Input, Typical Values are Test Results at 25oC, Unless Otherwise Specified (Continued) HI5808BIB -40oC TO 85oC PARAMETER Analog Input Common Mode Voltage Range (VIN+ + VIN-)/2 INTERNAL VOLTAGE REFERENCE Reference Output Voltage, VROUT (Loaded) Reference Output Current Reference Temperature Coefficient REFERENCE VOLTAGE INPUT Reference Voltage Input, VRIN Total Reference Resistance, RL Reference Current DC BIAS VOLTAGE DC Bias Voltage Output, VDC Max Output Current (Not To Exceed) DIGITAL INPUTS (CLK) Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic High Current, IIH Input Logic Low Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS (D0-D11) Output Logic Sink Current, IOL Output Logic Source Current, IOH Output Capacitance, COUT TIMING CHARACTERISTICS Aperture Delay, tAP Aperture Jitter, tAJ Data Output Delay, tOD Data Output Hold, t H Data Latency, tLAT Clock Pulse Width (Low) Clock Pulse Width (High) POWER SUPPLY CHARACTERISTICS Total Supply Current, ICC Analog Supply Current, AICC Digital Supply Current, DICC1 Output Supply Current, DICC2 Power Dissipation Offset Error PSRR, VOS Gain Error PSRR, FSE NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. With the clock off (clock low, hold mode). VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V VIN+ - VIN- = 2V AVCC or DVCC = 5V 5% AVCC or DVCC = 5V 5% 65 46 17 2 325 2 30 73 365 mA mA mA mA mW LSB LSB For a Valid Sample (Note 2) 10 MSPS Clock 10 MSPS Clock 45 45 5 5 8 8 50 50 3 55 55 ns ps (RMS) ns ns Cycles ns ns VO = 0.4V (Note 2) DVCC3 = 3.0V, VO = 0.4V VO = 2.4V (Note 2) DVCC3 = 3.0V, VO = 2.4V 1.6 -0.2 1.6 -0.2 5 mA mA mA mA pF VCLK = 5V VCLK = 0V 2.0 7 0.8 10.0 10.0 V V A A pF 2.3 1 V mA 3.5 7.8 450 V k A 3.5 50 1 V mA ppm/oC TEST CONDITIONS Differential Mode (Note 2) MIN 1 TYP 2.3 MAX 4 UNITS V
120
HI5808 Timing Waveforms
ANALOG INPUT
CLOCK INPUT
SN - 1
HN - 1
SN
HN
SN + 1
H N + 1 SN + 2
HN + 2
SN + 3 H N + 3 SN + 4 H N + 4 SN + 5
HN + 5
SN + 6
HN + 6
INPUT S/H
1ST STAGE
B1, N - 1
B1, N
B1, N + 1
B1, N + 2
B1, N + 3
B1, N + 4
B1, N + 5
2ND STAGE
B2, N - 2
B2, N - 1
B2, N
B2, N + 1
B2, N + 2
B2, N + 3
B2, N + 4
3RD STAGE 4TH STAGE
B3, N - 2
B3, N - 1
B3, N
B3, N + 1
B3, N + 2
B3, N + 3
B3, N + 4
B4, N - 3
B4, N - 2
B4, N - 1
B4, N
B4, N + 1
B4, N + 2
B4, N + 3
DATA OUTPUT
DN - 3
DN - 2 tLAT
DN - 1
DN
DN + 1
DN + 2
DN + 3
NOTES: 4. SN : N-th sampling period. 5. HN : N-th holding period. 6. BM, N : M-th stage digital output corresponding to N-th sampled input. 7. DN : Final data output corresponding to N-th sampled input. FIGURE 1. INTERNAL CIRCUIT TIMING
ANALOG INPUT tAP tAJ CLOCK INPUT
1.5V
1.5V
tOD tH 2.0V DATA N - 1 0.8V DATA N
DATA OUTPUT
FIGURE 2. INPUT-TO-OUTPUT TIMING
121
HI5808 Typical Performance Curves
11 fS = 10 MSPS TEMPERATURE = 25oC 60 SINAD (dB) 70 fS = 10 MSPS TEMPERATURE = 25oC
10 9 ENOB 8 7
50
40 6 5 1 10 INPUT FREQUENCY (MHz) 100 30 1
10 INPUT FREQUENCY (MHz)
100
FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT FREQUENCY
FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD) vs INPUT FREQUENCY
70 fS = 10 MSPS TEMPERATURE = 25oC 60 THD (dBc) SNR (dB)
-40 fS = 10 MSPS TEMPERATURE = 25oC -50
50
-60
40
-70
30 1
10 INPUT FREQUENCY (MHz)
-80 100 1
10 INPUT FREQUENCY (MHz)
100
FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT FREQUENCY
FIGURE 6. TOTAL HARMONIC DISTORTION (THD) vs INPUT FREQUENCY
80 fS = 10 MSPS TEMPERATURE = 25oC 70 SFDR (dBc)
11 2MHz 10 9 ENOB 5MHz 10MHz 20MHz 1MHz
60
8 7
fS = 10 MSPS TEMPERATURE = 25oC
50MHz
50 6 100MHz 40 1 10 INPUT FREQUENCY (MHz) 100 5 0.4 0.5 DUTY CYCLE (tCLK-LOW/tCLK) 0.6
FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs INPUT FREQUENCY
FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs CLOCK DUTY CYCLE AND INPUT FREQUENCY
122
HI5808 Typical Performance Curves
11 1MHz 10 9 ENOB 8 fS = 10 MSPS 7 50MHz 6 100MHz 5 -40 -20 0 40 20 TEMPERATURE (oC) 60 80 3.475 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 3.485 2MHz 5MHz 10MHz VROUT (V) 3.505 20MHz 3.515 VREFNOM
(Continued)
3.525
3.495
VREFLD
FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs TEMPERATURE AND INPUT FREQUENCY
FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT (VROUT) vs TEMPERATURE AND LOAD
326
70 60 ITOT
POWER DISSIPATION (mW)
324 fS = 10 MSPS VIN+ = VIN- = VDC CURRENT (mA) 50 AICC 40 30 20 318 10 DICC2 316 -40 -20 0 20 40 60 80 0 -40 -20 0 20 40 TEMPERATURE (oC) 60 80 DICC1 fS = 10 MSPS VIN+ = VIN- = VDC
322
320
TEMPERATURE (oC)
FIGURE 11. POWER DISSIPATION vs TEMPERATURE
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
0 -10 -20 OUTPUT LEVEL (dB) -30 -40 -50 -60 -70 -80 -90 -100 0
fIN = 1MHz, fS = 10 MSPS
1024 FREQUENCY BIN
2048
FIGURE 13. 4096 POINT FFT SPECTRAL PLOT
123
HI5808 Pin Descriptions
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME CLK DVCC1 DGND1 DVCC1 DGND1 AVCC AGND VIN+ VINVDC VROUT VRIN AGND AVCC D11 D10 D9 D8 D7 D6 DGND2 DVCC2 D5 D4 D3 D2 D1 D0 DESCRIPTION Sample Clock Input. Digital Supply (5.0V). Digital Ground. Digital Supply (5.0V). Digital Ground. Analog Supply (5.0V). Analog Ground. Positive Analog Input. Negative Analog Input. DC Bias Voltage Output. Reference Voltage Output. Reference Voltage Input. Analog Ground. Analog Supply (5.0V). FIGURE 14. ANALOG INPUT SAMPLE-AND-HOLD Data Bit 11 Output (MSB). Data Bit 10 Output. Data Bit 9 Output. Data Bit 8 Output. Data Bit 7 Output. Data Bit 6 Output. Digital Output Ground. Digital Output Supply (3.0V to 5.0V). Data Bit 5 Output. Data Bit 4 Output. Data Bit 3 Output. Data Bit 2 Output. Data Bit 1 Output. Data Bit 0 Output (LSB).
VIN VIN +
capacitors. In the next clock phase, 2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op-amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-and-hold function but will also convert a single-ended input to a fullydifferential output for the converter core. During the sampling phase, the VIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 100MHz for the converter. 1 1 2 1
CS CS
CH
1
-+ +-
VOUT + VOUT -
1
CH
1
As illustrated in the functional block diagram and the timing diagram in Figure 1, three identical pipeline subconverter stages, each containing a four-bit flash converter, a four-bit digital-to-analog converter and an amplifier with a voltage gain of 8, follow the S/H circuit with the fourth stage being only a 4-bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock signal, with the result that alternate stages in the pipeline will perform the same operation. The digital output of each of the three identical 4-bit subconverter stages is a four-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the three identical four-bit subconverter stages with the corresponding output of the fourth stage flash converter before applying the sixteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final twelve bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus on the 3rd cycle of the clock after the analog sample is taken. This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output on the following clock pulse. The digital output data is synchronized to the external sampling clock with an output latch. The output of the digital error correction circuit is available in offset binary format (see Table 1, A/D Code Table).
Detailed Description
Theory of Operation The HI5808 is a 12-bit fully differential sampling pipeline A/D converter with digital error correction. Figure 14 depicts the circuit for the front end differential-in-differential-out sampleand-hold (S/H). The switches are controlled by an internal clock which is a non-overlapping two phase signal, 1 and 2 , derived from the master clock. During the sampling phase, 1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of 1 the input signal is sampled on the bottom plates of the sampling 124
HI5808
TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE DIFFERENTIAL INPUT VOLTAGE MSB (USING INTERNAL REFERENCE) D11 +1.99976V 1.99878V 732.4V -244.1V -1.99829V -1.99927V 1 1 1 0 0 0 LSB D10 1 1 0 1 0 0 D9 1 1 0 1 0 0 D8 1 1 0 1 0 0 D7 1 1 0 1 0 0 D6 1 1 0 1 0 0 D5 1 1 0 1 0 0 D4 1 1 0 1 0 0 D3 1 1 0 1 0 0 D2 1 1 0 1 0 0 D1 1 1 0 1 0 0 D0 1 0 0 1 1 0
CODE CENTER DESCRIPTION +Full Scale (+FS) - 1/4 LSB +FS - 11/4 LSB + 3/4 LSB - 1/4 LSB -FS + 13/4 LSB -Full Scale (-FS) + 3/4 LSB
The voltages listed above represent the ideal center of each offset binary output code shown.
Internal Reference Generator, VROUT and VRIN The HI5808 has an internal reference generator, therefore, no external reference voltage is required. VROUT must be connected to VRIN when using the internal reference voltage. The HI5808 can be used with an external reference. The converter requires only one external reference voltage connected to the VRIN pin with VROUT left open. The HI5808 is tested with VRIN equal to 3.5V. Internal to the converter, two reference voltages of 1.3V and 3.3V are generated for a fully differential input signal range of 2V. In order to minimize overall converter noise, it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN . Analog Input, Differential Connection The analog input to the HI5808 can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 15) will give the best performance for the converter. A 2.3V DC bias voltage source, VDC , half way between the top and bottom internal reference voltages, is made available to the user to help simplify circuit design when using a differential input. This low output impedance voltage source is not designed to be a reference but makes an excellent bias source and stays within the analog input common mode voltage range over temperature. The difference between the converter's two internal voltage references is 2V. For the AC coupled differential input, (Figure 15), if VIN is a 2VP-P sinewave with -VIN being 180 degrees out of phase with VIN , then VIN+ is a 2VP-P sinewave riding on a DC bias voltage equal to VDC and VIN- is a 2VP-P sinewave riding on a DC bias voltage equal to VDC. Consequently, the converter will be at positive full scale, all 1s digital data output code, when the VIN+ input is at VDC +1V and the VIN- input is at VDC -1V (VIN+ - VIN- = 2V). Conversely, the ADC will be at negative full scale, all 0s digital data output code, when the VIN+ input is equal to VDC - 1V and VIN- is at VDC + 1V (VIN+ - VIN- = -2V). From this, the converter is seen to have a peak-to-peak differential analog input voltage range of 2V. The analog input can be DC coupled (Figure 16) as long as the inputs are within the analog input common mode voltage range (1.0V VDC 4.0V).
VIN VDC R C VIN+ HI5808 VDC
VIN
VIN+ HI5808 VDC
-VIN
VIN-
-VIN FIGURE 15. AC COUPLED DIFFERENTIAL INPUT
VDC
R VIN-
Since the HI5808 is powered off a single +5V supply, the analog input must be biased so it lies within the analog input common mode voltage range of 1.0V to 4.0V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. 125
FIGURE 16. DC COUPLED DIFFERENTIAL INPUT
The resistors, R, in Figure 16 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from VIN+ to VIN- will help filter any high
HI5808
frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. Analog Input, Single-Ended Connection The configuration shown in Figure 17 may be used with a single ended AC coupled input. Sufficient headroom must be provided such that the input voltage never goes above +5V or below AGND .
VIN VIN+
Digital I/O and Clock Requirements The HI5808 provides a standard high-speed interface to external TTL/CMOS logic families. The digital CMOS clock input has TTL level thresholds. The low input bias current allows the HI5808 to be driven by CMOS logic. The digital CMOS outputs have a separate digital supply. This allows the digital outputs to operate from a 3.0V to 5.0V supply. When driving CMOS logic, the digital outputs will swing to the rails. When driving standard TTL loads, the digital outputs will meet standard TTL level requirements even with a 3.0V supply. In order to ensure rated performance of the HI5808, the duty cycle of the clock should be held at 50% 5%. It must also have low jitter and operate at standard TTL levels. Performance of the HI5808 will only be guaranteed at conversion rates above 0.5 MSPS. This ensures proper performance of the internal dynamic circuits. Supply and Ground Considerations The HI5808 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5808 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply and ground pins should be isolated by ferrite beads from the digital supply and ground pins. Refer to the Application Note AN9214, "Using Intersil High Speed A/D Converters" for additional considerations when using high speed converters.
VDC
HI5808
VIN-
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
Again, the difference between the two internal voltage references is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a 4VP- P sinewave riding on a positive voltage equal to VDC. The converter will be at positive full scale when VIN+ is at VDC + 2V (VIN+ - VIN- = 2V) and will be at negative full scale when VIN+ is equal to VDC - 2V (VIN+ - VIN- = -2V). In this case, VDC could range between 2V and 3V without a significant change in ADC performance. The simplest way to produce VDC is to use the VDC bias voltage output of the HI5808. The single ended analog input can be DC coupled (Figure 18) as long as the input is within the analog input common mode voltage range.
VIN VDC R C HI5808 VIN+
Static Performance Definitions
Offset Error (VOS) The midscale code transition should occur at a level 1/4 LSB above half-scale. Offset is defined as the deviation of the actual code transition from this point. Full-Scale Error (FSE)
VDC
VIN -
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
The last code transition should occur for an analog input that is 3/4 LSB below positive full scale with the offset error removed. Full-scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Power Supply Rejection Ratio (PSRR) Each of the power supplies are moved plus and minus 5% and the shift in the offset and gain error (in LSBs) is noted.
The resistor, R, in Figure 18 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from VIN+ to VIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source will give better overall system performance if it is first converted to differential before driving the HI5808. 126
HI5808 Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5808. A low distortion sine wave is applied to the input, it is coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. SNR and SINAD are quoted in dB. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Signal-to-Noise Ratio (SNR) Full Power Input Bandwidth (FPBW) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency, fS/2, excluding DC. Effective Number Of Bits (ENOB) The effective number of bits (ENOB) is calculated from the SINAD data by:
ENOB = ( SINAD + V CORR -1.76 )/6.02,
Transient Response Transient response is measured by providing a full-scale transition to the analog input of the ADC and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy. Over-Voltage Recovery Over-voltage Recovery is measured by providing a full-scale transition to the analog input of the ADC which overdrives the input by 200mV, and measuring the number of cycles it takes for the output code to settle within 12-bit accuracy.
Full power input bandwidth is the analog input frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sinewave. The input sinewave has an amplitude which swings from -fS to +fS . The bandwidth given is measured at the specified sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2, Input-To-Output Timing, for these definitions. Aperture Delay (tAP) Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays.
Aperture Jitter (tAJ)
where: VCORR = 0.5dB. VCORR adjusts the ENOB for the amount the input is below full scale. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the fundamental input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the applicable harmonic component to the RMS value of the fundamental input signal. Spurious Free Dynamic Range (SFDR) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component in the spectrum below fS/2. Intermodulation Distortion (IMD) Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present at the inputs. The ratio of the measured signal to the distortion terms is calculated. The terms included in the calculation are (f1 + f2), (f1 - f2), (2f1), (2f2), (2f1 + f2), (2f1 - f2), (f1 + 2f2), (f1 - 2f2). The ADC is tested with each tone 6dB below full scale. 127
Aperture Jitter is the RMS variation in the aperture delay due to variation of internal clock path delays. Data Hold Time (tH) Data hold time is the time to where the previous data (N - 1) is no longer valid. Data Output Delay Time (tOD) Data output delay time is the time to where the new data (N) is valid. Data Latency (tLAT) After the analog sample is taken, the digital data is output on the bus at the third cycle of the clock. This is due to the pipeline nature of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input sample by 3 clock cycles.
HI5808
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